The present invention relates generally to electronic amplifier circuits, and more particularly to class B amplifier circuits.
Class A amplifier circuits often contain two parallel input stages. Each input stage may have a power operational amplifier that is configured as a unity gain voltage follower. Each input stage typically drives a high current output transistor. The output transistors are connected in common source configuration to operate as a complementary class A output stage, which conducts a quiescent bias current. An example of a class A amplifier circuit 100 is shown in FIG. 1.
FIG. 1 is a schematic of a conventional class A amplifier circuit (100). The class A amplifier circuit 100 includes amplifiers X1 and X2 and power transistors M1 and M2.
Amplifier X1 has an inverting input that is coupled to node Vin, a non-inverting input that is coupled to node Vout, and an output that is coupled to node N1. Amplifier X2 has an inverting input that is coupled to node Vin, a non-inverting input that is coupled to node Vout, an output that is coupled to node N2. Transistor M1 has a source that is coupled to a first voltage (such as VDD), a gate that is coupled to node N1, and the drain that is coupled to node Vout. Transistor M2 has a source that is coupled to a second voltage (such as ground), a gate that is coupled to node N2, and a drain that is coupled to node Vout.
Amplifiers X1 and X2 form the input stage of circuit 100. Amplifiers X1 and X2 are arranged as voltage followers to produce voltages at nodes N1 and N2 in response to the voltage present at node Vin. Transistors M1 and M2 conduct a quiescent bias current, notwithstanding the gate voltages at nodes N1 and N2 or any load that may be coupled to node Vout.
The present invention is directed towards a circuit for providing class B amplification with a rail-to-rail output swing while having a small deadband. The circuit has two parallel input stages that each use an amplifier configured as a unity gain voltage follower. The output of each stage drives a high current output transistor. The output transistors are complementary transistors arranged in a common source configuration. The common source configuration operates as a complementary class B amplifier, which conducts no quiescent bias current. An offset voltage is introduced in each input stage, which creates a small deadband in the output voltage as it switches between sinking current and sourcing current. The offset voltage is selected to ensure that the output transistors are not both simultaneously activated.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrated embodiments of the invention, and to the appended claims.